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DATA SHEET
MOS INTEGRATED CIRCUIT
PD78001B(A), 78002B(A)
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD78001B(A)/78002B(A) are products in the PD78002 subseries within the 78K/0 series. The PD78001B(A)/78002B(A) have various peripheral hardware such as timer, serial interface and interrupt function. A one-time PROM or EPROM product, the PD78P014, capable of operating in the same power supply voltage range as that of the mask ROM product and other development tools is provided. Functions are described in detail in the following User's Manual, which should be read when carrying out design work. PD78002, 78002Y Series User's Manual: IEU-1334
FEATURES
* The PD78001B, in comparison with the 78002B, is a higher reliability device, as a result of a more comprehensive quality assurance program (Refer to Quality Grade on NEC Semiconductor Devices (IEI-1209)) * Large on-chip ROM & RAM
Item Product Name Program Memory (ROM) 8K bytes 16K byte Data Memory (Internal High-Speed RAM) 256 bytes 384 bytes * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP ( 14 mm) Package
PD78001B(A) PD78002B(A)
* External memory expansion space: 64K bytes * Instruction execution time can be varied from high-speed (0.4 s) to ultra-low-speed (122 s) * I/O ports: 53 (N-ch open-drain : 4) * Serial interface : 1 channel * Timer: 4 channels * Operating voltage range : 2.7 to 6.0 V
APPLICATION
Transmission equipment control device, gas detector circuit breaker, safety devices, etc.
The information in this document is subject to change without notice.
Document No. IC-3599 (O.D. No. IC-9078) Date Published February 1995 P Printed in Japan
(c)
1995
PD78001B(A), 78002B(A)
ORDERING INFORMATION
Part Number Package 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (s 14 mm) s 64-pin plastic shrink DIP (750 mil) 64-pin plastic QFP (s 14 mm) s Quality Grade Special Special Special Special
PD78001BCW (A)-xxx PD78001BGC (A)-xxx-AB8 PD78002BCW (A)-xxx PD78002BGC (A)-xxx-AB8
Remark xxx indicates ROM code No.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
Difference between the PD78001B(A), 78002B(A) and the PD78001B, 78002B.
Product Name Item Quality Grade
PD78001B(A), 78002B(A)
PD78001B, 78002B
Special
Standard
2
PD78001B(A), 78002B(A)
78K/0 SERIES PRODUCT DEVELOPMENT
These products are a further development in the 78K/0 Series. The designations appearing inside the boxes are subseries names.
Products in Volume Production Products under Development For control 100-pin 80-pin 64-pin 64-pin 64-pin 42/44-pin
2 Y series products are compatible with I C bus.
PD78078 PD78054 PD78018F PD78014 PD78002 PD78083
PD78078Y PD78054Y PD78018FY PD78014Y PD78002Y
Timer added to the PD78054, external interface functions UART and D/A added to the PD78014, I/O enhanced Low-voltage (1.8 V) operation version of the PD78014, with enhanced ROM and RAM variations A/D and 16-bit timer added to the PD78002 Basic subseries for control Internal UART, low-voltage (1.8 V) operation possible
78K/0 Series For FIP(R) driving 100-pin PD780208 80-pin PD78044A 64-pin PD78024 For LCD driving 100-pin I/O, FIP C/D of the PD78044A enhanced, display output total: 53 6-bit U/D counter added to the PD78024, display output total: 34 Basic subseries for FIP driving, display output total: 26
PD78064
For IEBus
TM
PD78064Y
Subseries for LCD driving, internal UART
80-pin
PD78098
IEBus controller added to the PD78054
The major functional differences among the subseries are shown below.
Function Name For Control 8-bit 16-bit 1ch Timer A/D Watch 1ch Watchdog 1ch 8-bit x 8ch D/A VDD MIN. Value 1.8 V 2.0 V 1.8 V 2.7 V -- -- 2ch 1ch 1ch 1ch -- 8-bit x 8ch 8-bit x 8ch -- 1ch 1ch (UART: 1ch) 2ch 33 74 68 54 2ch 1ch 1ch 1ch 8-bit x 8ch 8-bit x 8ch -- 2ch (UART: 1ch) 57 2.0 V -- 1.8 V 2.7 V -- --
Serial Interface
I/O
External Expansion
PD78078 PD78054 PD78018F PD78014 PD78002 PD78083
4ch 2ch
8-bit x 2ch 3ch (UART: 1ch)
88 69
C
--
2ch
53
For FIP (R) driving
PD780208 PD78044A PD78024
For LCD driving For IEBusTM
PD78064 PD78098
2ch
1ch
1ch
1ch
8-bit x 2ch 3ch (UART: 1ch)
69
2.7 V
C
3
PD78001B(A), 78002B(A)
OVERVIEW OF FUNCTION
Product Name Item Internal memory ROM Internal highspeed RAM 64K bytes 8 bits x 32 registers (8 bits x 8 registers x 4 banks) On-chip instruction execution time cycle modification function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (at 10.0 MHz operation) 122 s (at 32.768 kHz operation)
PD78001B(A)
8K bytes 256 bytes
PD78002B(A)
16K bytes 384 bytes
Memory space General registers Instruction cycle When main system clock selected When subsystem clock selected Instruction set
* 16-bit operation * Bit manipulation (set, reset, test, boolean operation) * BCD correction, etc. Total * CMOS input * CMOS I/O * N-channel open-drain I/O (15 V withstand voltage) : 53 : 02 : 47 : 04
I/O ports
Serial interface Timer
* 3-wire/SBI/2-wire mode selectable * 8-bit timer/event counter * Watch timer * Watchdog timer 2 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock 10.0 MHz operation), 32.768 kHz (at subsystem clock 32.768 kHz operation) 2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 10.0 MHz operation) Internal : 5 External : 4 Internal : 1 : 2 channels : 1 channel : 1 channel
Timer output Clock output
Buzzer output Vectored interrupts Maskable interrupts Non-maskable interrupt Software interrupt Test input
Internal : 1
Internal : 1 External : 1 VDD = 2.7 to 6.0 V -40 to +85C * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (s 14 mm) s
Operating voltage range Operating ambient temperature range Package
4
PD78001B(A), 78002B(A)
CONTENTS 1. 2. 3. PIN CONFIGURATION (TOP VIEW) ..................................................................................................... BLOCK DIAGRAM ................................................................................................................................... 6 9
PIN FUNCTIONS ..................................................................................................................................... 10
3.1 3.2 3.3 PORT PINS ...................................................................................................................................................... 10 OTHER PINS ................................................................................................................................................... 12 PIN I/O CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PINS ...................................... 13
4. 5.
MEMORY SPACE .................................................................................................................................... 15 PERIPHERAL HARDWARE FUNCTION FEATURES ............................................................................ 16
5.1 5.2 5.3 5.4 5.5 5.6 PORTS .............................................................................................................................................................. 16 CLOCK GENERATOR ...................................................................................................................................... 17 TIMER/EVENT COUNTER .............................................................................................................................. 18 CLOCK OUTPUT CONTROL CIRCUIT ......................................................................................................... 20 BUZZER OUTPUT CONTROL CIRCUIT ....................................................................................................... 20 SERIAL INTERFACES ..................................................................................................................................... 21
6.
INTERRUPT FUNCTIONS AND TEST FUNCTIONS .......................................................................... 22
6.1 6.2 INTERRUPT FUNCTIONS ............................................................................................................................... 22 TEST FUNCTIONS .......................................................................................................................................... 25
7. 8. 9.
EXTERNAL DEVICE EXPANSION FUNCTIONS ................................................................................. 26 STANDBY FUNCTIONS ......................................................................................................................... 26 RESET FUNCTION .................................................................................................................................. 26
10. INSTRUCTION SET ................................................................................................................................ 27 11. ELECTRICAL SPECIFICATIONS ............................................................................................................. 30 12. CHARACTERISTIC CURVE (REFERENCE VALUES) ........................................................................... 48 13. PACKAGE DRAWINGS ........................................................................................................................... 52 14. RECOMMENDED SOLDERING CONDITIONS ..................................................................................... 56 APPENDIX A. DEVELOPMENT TOOLS ...................................................................................................... 57 APPENDIX B. RELATED DOCUMENTS ...................................................................................................... 59
5
PD78001B(A), 78002B(A)
1. PIN CONFIGURATION (TOP VIEW)
64-Pin Plastic Shrink DIP (750 mil)
P20 P21 P22 P23 P24 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7 P50/A8 P51/A9 P52/A10 P53/A11 P54/A12 P55/A13 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
IC3 IC2 P17 P16 P15 P14 P13 P12 P11 P10 IC1 P04/XT1 XT2 IC0 X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0 RESET P67/ASTB P66/WAIT P65/WR P64/RD P63 P62 P61 P60 P57/A15 P56/A14
Remark
Always connect the IC0, IC1 and IC3 (Internally Connected) pins to VSS directly. Always connect the IC2 pin to VDD directly.
PD78001BCW(A)- x x x PD78002BCW(A)- x x x
6
PD78001B(A), 78002B(A)
64-Pin Plastic QFP (s 14 mm) s
P26/SO0/SB1
P25/SI0/SB0
P27/SCK0
P24
P23
P22
P21
P20
P17
P16
P15
P14
P13
P30 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 VSS P40/AD0 P41/AD1 P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6
1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
P12
IC3
IC2
P11 P10 IC1 P04/XT1 XT2 IC0 X1 X2 VDD P03/INTP3 P02/INTP2 P01/INTP1 P00/INTP0 RESET P67/ASTB P66/WAIT
PD78001BGC(A)- x x x -AB8 PD78002BGC(A)- x x x -AB8
10 11 12 13 14 15
33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
P56/A14
P57/A15
P47/AD7
P64/RD
P60
P61
P62
P63
Remark
Always connect the IC0, IC1 and IC3 (Internally Connected) pins to VSS directly. Always connect the IC2 pin to VDD directly.
P65/WR
VSS
7
PD78001B(A), 78002B(A)
P00 to P04 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 INTP0 to INTP3 TI1, TI2 TO1, TO2 SB0, SB1 SI0 SO0 SCK0
: : : : : : : : : : : : : :
Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Interrupt From Peripherals Timer Input Timer Output Serial Bus Serial Input Serial Output Serial Clock
PCL BUZ AD0 to AD7 A8 to A15 RD WR WAIT ASTB X1, X2 XT1, XT2 RESET VDD VSS IC0 to IC3
: : : : : : : : : : : : : :
Programmable Clock Buzzer Clock Address/Data Bus Address Bus Read Strobe Write Strobe Wait Address Strobe Crystal (Main System Clock) Crystal (Subsystem Clock) Reset Power Supply Ground Internally Connected
8
PD78001B(A), 78002B(A)
2. BLOCK DIAGRAM
TO1/P31 TI1/P33 TO2/P32 TI2/P34
8-bit TIMER/ EVENT COUNTER 1
PORT0
P00 P01-P03 P04
8-bit TIMER/ EVENT COUNTER 2
PORT1
P10-P17
WATCHDOG TIMER 78K/0 CPU CORE WATCH TIMER SI0/SB0/P25 SO0/SB1/P26 SCK0/P27 INTP0/P00 - INTP3/P03 ROM
PORT2
P20-P27
PORT3
P30-P37
SERIAL INTERFACE 0
PORT4
P40-P47
INTERRUPT CONTROL RAM
PORT5
P50-P57
BUZ/P36
BUZZER OUTPUT
PORT6
P60-P67
PCL/P35
CLOCK OUTPUT CONTROL
AD0/P40AD7/P47 EXTERNAL ACCESS A8/P50A15/P57 RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET X1 X2 XT1/P04 XT2
VDD
VSS
IC0IC3
SYSTEM CONTROL
Remark
Internal ROM & RAM capacity varies depending on the product.
9
PD78001B(A), 78002B(A)
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
I/O Input Input/ output Port 0 5-bit I/O port Function Input only Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input only Port 1 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. After Reset Input Input DualFunction Pin INTP0 INTP1 INTP2 INTP3 Input Input/ output Input XT1 -
Pin Name P00 P01 P02 P03 P04* P10 to P17
P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 to P47
Input/ output
Port 2 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software.
Input
- - - - - SI0/SB0 SO0/SB1 SCK0
Input/ output
Port 3 8-bit input/output port. Input/output can be specified in bit-wise. When used as an input port, pull-up resistor can be used by software.
Input
- TO1 TO2 TI1 TI2 PCL BUZ -
Input/ output
Port 4 8-bit input/output port. Input/output can be specified in 8-bit unit. When used as an input port, pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection.
Input
AD0 to AD7
* When using the P04/XT1 pins as an input port, set 1 to bit 6 (FRC) of the processor control register. (Do not use the on-chip feedback register of the subsystem clock oscillator.)
10
PD78001B(A), 78002B(A)
3.1
PORT PINS (2/2)
I/O Input/ output Function Port 5 8-bit input/output port. LED can be driven directly. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Port 6 8-bit input/output port. Input/output can be specified bit-wise. N-ch open-drain input/output port. Onchip pull-up resistor can be specified by mask option. LED can be driven directly. When used as an input port, pull-up resistor can be used by software. After Reset Input DualFunction Pin A8 to A15
Pin Name P50 to P57
P60 P61 P62 P63 P64 P65 P66 P67
Input/ output
Input
RD WR WAIT ASTB
Caution
When pull-up resistors are not used (specified by mask option), the low-level input leak current increases with -200 A (MAX.) under either of the following conditions. 1 When the external device expansion function is used and a low-level is input to the pin. 2 During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode register (PM6).
11
PD78001B(A), 78002B(A)
3.2
OTHER PINS
I/O Input Function Effective edge (rising edge, falling edge, or both rising edge and falling edge) can be specified. External interrupt input. Falling edge detection external interrupt input. Input Output Input /output Input /output Serial interface serial clock input/output. Input Serial interface serial data input. Serial interface serial data output. Serial interface serial data input/output. Input Input Input After Reset Input DualFunction Pin P00 P01 P02 P03 P25/SB0 P26/SB1 P25/SI0 P26/SO0 P27
Pin Name INTP0 INTP1 INTP2 INTP3 SI0 SO0 SB0 SB1 SCK0
TI1 TI2 TO1 TO2 PCL BUZ AD0 to AD7
Input
External count clock input to 8-bit timer (TM1). External count clock input to 8-bit timer (TM2).
Input
P33 P34
Output
8-bit timer (TM1) output. 8-bit timer (TM2) output.
Input
P31 P32
Output Output Input /output
Clock output (for main system clock, subsystem clock trimming). Buzzer output. Low-order address/data bus at external memory expansion.
Input Input Input
P35 P36 P40 to P47
A8 to A15 RD WR WAIT ASTB
Output Output
High-order address bus at external memory expansion. External memory read operation strobe signal output. External memory write operation strobe signal output.
Input Input
P50 to P57 P64 P65
Input Output
Wait insertion at external memory access. Strobe output which latches the address information output at port 4 and port 5 to access external memory.
Input Input
P66 P67
RESET X1 X2 XT1 XT2 VDD VSS IC0 to IC3
Input Input -- Input -- -- -- --
System reset input. Main system clock oscillation crystal connection.
-- -- --
-- -- -- P04 -- -- -- --
Subsystem clock oscillation crystal connection.
Input --
Positive power supply. Ground potential. Internal connection. IC0/IC1/IC3 and IC2 should be connected directly to VSS VDD, respecitively.
-- -- --
12
PD78001B(A), 78002B(A)
3.3 PIN I/O CIRCUIT AND RECOMMENDED CONNECTION OF UNUSED PINS The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, see Fig. 3-1. Table 3-1 Input/Output Circuit Type of Each Pin
Input/Output Circuit Type 2 8-A Input Input/output
Pin Name P00/INTP0 P01/INTP1 P02/INTP2 P03/INTP3 P04/XT1 P10 to P17 P20 to P24 P25/SI0/SB0 P26/SO0/SB1 P27/SCK0 P30 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P37 P40/AD0 to P47/AD7 P50/A8 to P57/A15 P60 to P63 P64/RD P65/WR P66/WAIT P67/ASTB RESET XT2 IC0, IC1, IC3 IC2
I/O
Recommended Connection when Not Used Connected to VSS . Connected to VSS through resistor independently.
16 5-A
Input Input/output
Connected to VDD or VSS . Connected to VDD or VSS through resistor independently.
10-A
5-A
8-A
5-A
5-E 5-A 13-B 5-A
Connected to VDD through resistor independently. Connected to VDD or VSS through resistor independently. Connected to VDD through resistor independently. Connected to VDD or VSS through resistor independently.
2 16 --
Input --
-- Leave open. Connected to VSS directly. Connected to VDD directly.
13
PD78001B(A), 78002B(A)
Fig. 3-1 Pin Input/Output Circuits
Type 10-A pullup enable IN data open drain output disable Schmitt-Triggered Input with Hysteresis Characteristic V DD P-ch IN / OUT N-ch V DD P-ch
Type 2
Type 5-A pullup enable V DD data output disable input enable Type 5-E pullup enable data output disable
V DD P-ch
Type 13-B Mask Option data output disable N-ch V DD IN / OUT RD P-ch
V DD IN / OUT
P-ch N-ch
Middle-High Voltage Input Buffer
V DD P-ch V DD P-ch IN / OUT N-ch
Type 16 feedback cut-off P-ch
XT1
XT2
Type 8-A pullup enable V DD data output disable
V DD P-ch
P-ch IN / OUT N-ch
14
PD78001B(A), 78002B(A)
4. MEMORY SPACE
The memory map of PD78001B(A)/78002B(A) is shown in Fig. 4-1. Fig. 4-1 Memory Map
FFFFH Special Function Registers (SFR) 256 x 8 Bits FF00H FEFFH FEE0H FEDFH General Registers 32 x 8 Bits
Internal High-Speed RAM*
mmmmH mmmmH-1
nnnnH Program Area
Data Memory Space
Use Prohibited
1000H 0FFFH CALLF Entry Area 0800H 07FFH Program Area
FA80H FA7FH Program Memory Space nnnnH+1 nnnnH
External Memory
0080H 007FH CALLT Table Area 0040H 003FH
Internal ROM* 0000H 0000H
Vector Table Area
Remark
Shaded area indicates internal memory.
* Intermal ROM and internal high-speed RAM capacities vary depending on the product (see the table below).
Internal ROM Product Name End Address nnnnH 1FFFH 3FFFH Internal High-Speed RAM Start Address mmmmH FE00H FD80H
PD78001B(A) PD78002B(A)
15
PD78001B(A), 78002B(A)
5
PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 PORTS The I/O port has the following three types. * CMOS input (P00, P04) * CMOS input/output (P01 to P03, port 1 to port 5, P64 to P67) * N-ch open-drain input/output (15V withstand voltage) (P60 to P63) Total : 2
: 47 : 4
: 53
Table 5-1 Functions of Ports
Port Name Port 0 Pin Name P00, P04 P01 to P03 Port 1 Port 2 Port 3 Port 4 P10 to P17 P20 to P27 P30 to P37 P40 to P47 Dedicated Input port Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Input/output ports. Input/output can be specified in 8-bit units. When used as an input port, pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. LED can be driven directly. N-ch open-drain input/output port. Input/output can be specified bit-wise. On-chip pull-up resistor can be specified by mask option. LED can be driven directly. Input/output ports. Input/output can be specified bit-wise. When used as an input port, pull-up resistor can be used by software. Function
Port 5
P50 to P57
Port 6
P60 to P63
P64 to P67
Caution
When pull-up resistors are not used (specified by mask option), low-level input leak current increases with -200 A (MAX.) under either of the following conditions. 1 When the external device expansion function is used and a low-level is input to the pin. 2 During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode register (PM6).
16
PD78001B(A), 78002B(A)
5.2 CLOCK GENERATOR There are two types of clock generator: main system clock and subsystem clock. The instruction exection time can be changed. * 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (mainsystem clock: at 10.0 MHz operation) * 122 s (subsystem clock: at 32.768 KHz operation)
Fig. 5-1 Clock Generator Block Diagram
XT1/P04 XT2
Subsystem fXT Clock Osicillator Prescaler
Watch Timer Clock Output Function
X1 X2
Main System Clock Osicillator
fX
Prescaler
Clock to Peripheral Hardware fX 24
fX 2 STOP
fX 22
fX 23
Selector
Standby Control Circuit
Wait Control Circuit
CPU Clock (fCPU)
INTP0 Sampling Clock
17
PD78001B(A), 78002B(A)
5.3 TIMER/EVENT COUNTER The following four channels are incorporated in the timer/event counter. * 8-bit timer/event counter * Watch timer * Watchdog timer : 2 channels : 1 channel : 1 channel
Table 5-2 Types and Features of Timer/Event Counter
8-bit Timer/Event Counter
Watch Timer
Watchdog Timer
Type
Interval timer External event counter
2 channels 2 channels 2 outputs 2 outputs 2
1 channel - - - 2
1 channel - - - 1
Functions
Timer output Sqare wave output Interrupt request
Fig. 5-2 8-Bit Timer/Enent Counter Block Diagram
Internal Bus INTTM1 8-Bit Compare Register (CR10)
8-Bit Compare Register (CR20) Selector Match
Match
Output Control Circuit
TO2/P32 INTTM2
fX/2 - fX/210 fX/212 TI1/P33 Selector 8-Bit Timer Register 1 (TM1) Selector Clear 8-Bit Timer Register 2 (TM2) Clear fX/2 - fX/210 fX/212 TI1/P34 Output Control Circuit Internal Bus Selector Selector
TO1/P31
18
PD78001B(A), 78002B(A)
Fig. 5-3 Watch Timer Block Diagram
fX/2 8 Selector fXT
Selector fW Prescaler
5-Bit Counter
fW 214 Selector fW 213 INTWT
fW 24
fW 25
fW 26
fW 27
fW 28
fW 29
Selector
INTTM3
Fig. 5-4 Watchdog Timer Block Diagram
fW 24 fW 25 fW 26 fW 27
Prescaler fW 28 fW 29 fW fW 210 212
INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request
19
PD78001B(A), 78002B(A)
5.4 CLOCK OUTPUT CONTROL CIRCUIT The clock with the following frequencies can be output for clock output. * 39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz (Main system clock: at 10.0 MHz operation) * 32.768 kHz (Subsystem clock: at 32.768 kHz operation) Fig. 5-5 Clock Output Control Block Diagram
fX/2 3 fX/2 4 fX/2 5 fX/2 6 fX/2 7 fX/2 8 fXT Selector Synchronization Circuit Output Control Circuit PCL/P35
5.5 BUZZER OUTPUT CONTROL CIRCUIT The clock with the following frequencies can be output for buzzer output. * 2.4 kHz/4.9 kHz/9.8 kHz (Main system clock: at 10.0 MHz operation) Fig. 5-6 Buzzer Output Control Block Diagram
fX/210 fX/211 fX/212 Selector Output Control Circuit BUZ/P36
20
PD78001B(A), 78002B(A)
5.6 SERIAL INTERFACES There is one on-chip clocked serial interface. Serial Interface channel 0 has the following three modes. * 3-wire serial I/O mode * SBI (Serial Bus Interface) mode * 2-wire serial I/O mode : MSB/LSB-first switchable : MSB-first : MSB-first
Fig. 5-7 Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/P25 Selector SO0/SB1/P26 Serial I/O Shift Register 0 (SIO0) Output Latch
Selector
Bus Release/Command/ Acknowledge Detection Circuit Serial Counter
Busy/Acknowledge Output Circuit
SCK0/P27
Interrupt Request Signal Generator
INTCSI0
fX/22 - fX/2 9 Serial Clock Control Circuit Selector TO2
21
PD78001B(A), 78002B(A)
6. INTERRUPT FUNCTIONS AND DEST FUNCTIONS
6.1 INTERRUPT FUNCTIONS There are 11 interrupt functions of 3 different kinds as shown below. * Non-maskable interrupt * Maskable interrupt * Software interrupt : : : 1 9 1
Table 6-1 Interrrupt Source List
Interrupt Type Nonmaskable Maskable 0 Default Priority *1 Interrupt Source Name INTWDT Trigger Watchdog timer overflow (with nonmaskable interrupt selected) Watchdog timer overflow (with interval timer selected) Pin input edge detection External 0006H 0008H 000AH 000CH Serial interface channel 0 transfer end Reference time interval signal from watch timer 8-bit timer/event counter 1 match signal generation 8-bit timer/event counter 2 match signal generation BRK instruction execution Internal Internal 000EH 0012H B Internal/ External Internal Vector Table Adress 0004H Basic Configuration Type *2 A
INTWDT
B
1 2 3 4 5 6
INTP0 INTP1 INTP2 INTP3 INTCSI0 INTTM3
C D
7
INTTM1
0016H
8
INTTM2
0018H
Software
BRK
003EH
E
* 1. The default priority is the priority applicable when more priority than one maskable interrupt is generated. 0 is the highest and 11, the lowest. 2. Basic configuration types A to E correspond to (A) to (E) on the next page.
22
PD78001B(A), 78002B(A)
Fig. 6-1 Interrupt Function Basic Configuration (1/2) (A) Internal Non-Maskable Interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(B) Internal Maskable Interrupt
Internal Bus
MK
IE
PR
ISP
Interrupt Request
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(C) External Maskable Interrupt (INTP0)
Internal Bus
Sampling Clock Select Register (SCS)
External Interrupt Mode Register (INTM0)
MK
IE
PR
ISP
Interrupt Request
Sampling Clock
Edge Detector
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
23
PD78001B(A), 78002B(A)
Fig. 6-1 Interrupt Function Basic Configuration (2/2) (D) External Maskable Interrupt (Except INTP0)
Internal Bus
External Interrupt Mode Register (INTM0)
MK
IE
PR
ISP
Interrupt Request
Edge Detector
IF
Priority Control Circuit
Vector Table Address Generator Standby Release Signal
(E) Software Interrupt
Internal Bus
Interrupt Request
Priority Control Circuit
Vector Table Address Generator
Remarks
1. 2. 3. 4. 5.
IF
: Interrupt request flag
IE : Interrupt enable flag ISP : In-service priority flag MK : Interrupt mask flag PR : Priority spcification flag
24
PD78001B(A), 78002B(A)
6.2 TEST FUNCTIONS There are two test functions as shown in Table 6-2. Table 6-2 Test Source List
Test Source Internal/External Name INTWT NTPT4 Watch timer overflow Port 4 falling edge detection Trigger Internal External
Fig. 6-2 Test Function Basic Configuration
Internal Bus
MK
Test Input
IF
Standby Release Signal
Remarks
1. 2.
IF
: Test input flag
MK : Test mask flag
25
PD78001B(A), 78002B(A)
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion function is used to connect external devices to areas other than the internal ROM, RAM and SFR. Ports 4 to 6 are used for connection with external devices.
8. STANDBY FUNCTIONS
There are the following two standby functions to reduce the current dissipation. * HALT mode : The CPU operating clock is stopped. The average consumption current can be reduced by intermittent operation in combination with the normal operating mode. : The main system clock oscillation is stopped. The whole operation by the main system clock is stopped, so that the system operates with ultra-low power consumption using only the subsystem clock. Fig. 8-1 Standby Functions
* STOP mode
Main System Clock Operation Interrupt Request STOP Instruction Interrupt Request
CSS=1 CSS=0 HALT Instruction
Subsystem Clock Operation* HALT Instruction
Interrupt Request
STOP Mode (Main system clock oscillation stopped)
HALT Mode (Clock supply to CPU is stopped, oscillation)
HALT Mode* (Clock supply to CPU is stopped, oscillation)
*
The power consumption can be reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set the MCC to stop the main system clock. The STOP instruction cannot be used. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program by the program.
Caution
9. RESET FUNCTION There are the following two reset methods.
* External reset input by RESET pin. * Internal reset by watchdog timer runaway time detection.
26
PD78001B(A), 78002B(A)
10. INSTRUCTION SET
(1) 8-Bit Instruction MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ
2nd Operand #byte 1st Operand A ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP r MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP r1 sfr saddr MOV MOV ADD ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV PUSH POP [DE] [HL] MOV MOV ROR4 ROL4 [HL+byte] [HL+B] [HL+C] MOV MOV MOV DBNZ INC DEC DBNZ MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP MOV MOV XCH MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP A r* sfr saddr !addr16 PSW [DE] [HL] [HL+byte] [HL+B] [HL+C] MOV XCH ADD ADDC SUB SUBC AND OR XOR CMP INC DEC ROR ROL RORC ROLC $addr16 1 None
* Except r = A
27
PD78001B(A), 78002B(A)
(2) 16-Bit Instruction MOVW, XCHW ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand #word 1st Operand AX ADDW SUBW CMPW rp MOVW MOVW* INCW, DECW PUSH, POP sfrp saddrp !addr16 SP MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW XCHW MOVW MOVW MOVW MOVW AX rp* sfrp saddrp !addr16 SP None
* Only when rp = BC, DE, HL.
(3) Bit Operation Instruction MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
2nd Operand A.bit 1st Operand A.bit MOV1 BT BF BTCLR sfr.bit MOV1 BT BF BTCLR saddr.bit MOV1 BT BF BTCLR PSW.bit MOV1 BT BF BTCLR [HL].bit MOV1 BT BF BTCLR CY MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 MOV1 AND1 OR1 XOR1 SET1 CLR1 NOT1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 SET1 CLR1 sfr.bit saddr.bit PWS.bit [HL].bit CY $addr16 None
28
PD78001B(A), 78002B(A)
(4) Call Instruction/Branch Instruction CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF,BTCLR, DBNZ
2nd Operand AX 1st Operand Basic instruction Compound instruction BR CALL, BR CALLF CALLT BR, BC, BNC, BZ, BNZ BT, BF, BTCLR, DBNZ !addr16 !addr11 [addr5] $addr16
(5) Other Instruction ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
29
PD78001B(A), 78002B(A)
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 C)
Parameter Supply voltage Input voltage Symbol VDD VI1 VI2 Output voltage Output current high IOH VO 1 pin P10 to P17, P20 to P27, P30 to P37 total P01 to P03, P40 to P47, P50 to P57, P60 to P67 total Output current low 1 pin Peak value Effective value P40 to P47, P50 to P55 total Peak value Effective value IOL* P01 to P03, P56, P57, P60 to P67 total P01 to P03, P64 to P67 total P10 to P17, P20 to P27, P30 to P37 total Operating ambient temperature Storage temperature TA Peak value Effective value Peak value Effective value Peak value Effective value P00 to P04, P10 to P17, P20 to P27, P30 toP37 P40 to P47, P50 to P57, P64 to P67, X1, X2, XT2 P60 to P67 Open-drain -0.3 to +16 -0.3 to VDD + 0.3 -10 -15 -15 30 15 100 70 100 70 50 20 50 20 -40 to +85 V V mA mA mA mA mA mA mA mA mA mA mA mA mA C Test Conditions Rating -0.3 to + 7.0 -0.3 to VDD + 0.3 Unit V V
Tstg
-65 to +150
C
*
Effective value should be calculated as follows: [Effective value] = [Peak value] x duty
Caution
Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximuam ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded.
30
PD78001B(A), 78002B(A)
Capacitance (TA = 25 C, VDD = VSS = 0 V)
Parameter Input capacitance I/O capacitance f=1 MHz Unmeasured CIO pins returned to 0 V Symbol CIN Test Conditions f=1 MHz Unmeasured pins returned to 0 V P01 to P03, P10 to P17, P20 to P27, P30 to P37, P40 toP47, P50 to P57, P64 to P67 P60 to P63 20 pF 15 pF MIN. TYP. MAX. 15 Unit pF
Remark
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
Main System Clock Oscillation Circuit Characteristics (TA = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Recommended Circuit Parameter Test Conditions MIN. TYP. MAX. Unit
Ceramic resonator
X1 X2 VSS R1 C1 C2
Oscillator frequency (fX) *1
VDD = Oscillator voltage range
1
10
MHz
Oscillation stabilization time *2
After VDD reaches oscillator voltage range MIN.
4
ms
Crystal resonator
X1 X2 VSS
Oscillator frequency (fX) *1 1 8.38 10 MHz
C1
C2
Oscillation stabilization time *2
VDD = 4.5 to 6.0 V
10 ms 30
External clock
X1 input
X1
X2
frequency (fX) *1
1.0
10.0
MHz
PD74HCU04
X1 input high/low level width (tXH , tXL) 42.5 500 ns
*
1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristics" for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions
1.
When using the main system clock oscillator, wiring the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. * * * * * * Wiring should be as short as possible. Wiring should not cross other signal lines. Wiring should not be placed close to a varying high current. The potential of the oscillator capacitor ground should be the same as VSS. Do not ground wiring to a ground pattern in which a high current flows. Do not fetch a signal from the oscillator.
2.
When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program.
31
PD78001B(A), 78002B(A)
Subsystem Clock Oscillation Circuit Characteristics (TA = -40 to +85 C, VDD = 2.7 to 6.0 V)
Resonator Recommended Circuit
XT1 XT2 VSS R2 C3 C4
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Crystal resonator
Oscillator frequency (fXT) *1 VDD = 4.5 to 6.0 V
32
32.768
35
kHz
Oscillation stabilization time *2
1.2
2 s 10
External clock
XT1 input
XT1
XT2
frequency (fXT) *1
32
100
kHz
XT1 input high/low level width (tXTH , tXTL) 5 15
s
*
1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristics" for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillator voltage MIN.
Cautions
1.
When using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. * * * * * * Wiring should be as short as possible. Wiring should not cross other signal lines. Wiring should not be placed close to a varying high current. The potential of the oscillator capacitor ground should be the same as VSS. Do not ground wiring to a ground pattern in which a high current flows. Do not fetch a signal from the oscillator.
2.
The subsystem clock oscillation circuit is a circuit with a low amplification level, more prone to misoperation due to noise than the main system clock. When using the subsystem clock, special care is needed regarding the wiring method.
32
PD78001B(A), 78002B(A)
RECOMMENDED OSCILLATION CIRCUIT CONSTANT
Main System Clock Ceramic Resonator (TA = -40 to +85 C)
Manufacturer Murata m.f.g. Products CSB1000J CSB x x x x J CSA x . x x x MK CSA x . x x MG CST x . x x MG CSAx . x x MG CSTx . x x MGW CSAx . x x MG CSTx . x x MGW CSAx . x x MT CSTx . x x MTW Kyocera KBR-4.19MWS 4.19 KBR-4.19MKS KBR-4.19MSA 4.19 PBRC4.19A KBR-10.0M KBR-1000F 1.00 KBR-1000Y 100 100 2.2 2.7 6.0 10.0 33 33 - 2.7 6.0 - - - 2.7 6.0 6.01-10.0 On-chip On-chip 0 2.9 6.0 4.19-6.00 On-chip 30 On-chip 30 0 0 2.7 2.9 6.0 6.0 2.45-4.18 On-chip 30 On-chip 30 0 0 2.7 2.7 6.0 6.0 1.80-2.44 On-chip 30 On-chip 30 0 0 2.7 2.7 6.0 6.0 Frequency (MHz) 1.00 1.01-1.25 1.26-1.79 Recommended Oscillation Constant C1 (pF) 100 100 100 100 C2 (pF) 100 100 100 100 R1 (k) 6.8 4.7 0 0 Oscillation Voltage Range MIN. (V) 2.9 2.7 2.7 2.7 MAX. (V) 6.0 6.0 6.0 6.0
33
33
-
2.8
6.0
Remark x x x x , x . x x x , x . x x indicates frequency.
Subsystem Clock: Crystal Resonator (TA = -40 to +60 C)
Manufacturer Products DT-38 (1TA632E00, Load capacitance 6.3pF) Frequency (MHz) Recommended Circuit Constant C3 (pF) Daishinku corp. 32.768 8 C4 (pF) 8 R2 (k) 100 Oscillation Voltage Range MIN. (V) 2.7 MAX. (V) 6.0
Caution
Regarding the oscillator circuit constant, operation is guaranteed, but reliability is not guaranteed. Customers who require high reliability should directly consult the resonator manufacturer.
33
PD78001B(A), 78002B(A)
DC Characteristics (TA = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter Input voltage high VIH2 VIH3 VIH4 VIH5 Symbol Test Conditions P10 to P17, P21, P23, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P64 to P67 P00 to P03, P20, P22, P24 to P27, P33, P34, RESET P60 to P63 X1, X2 XT1/P04, XT2 VDD = 4.5 to 6.0 V Open-drain 0.8 VDD 0.7 VDD VDD-0.5 VDD-0.5 VDD-0.3 Input voltage low VIL2 VIL3 VIL1 P10 to P17, P21, P23, P30 to P32, P35 to P37 P40 to P47, P50 to P57, P64 to P67 P00 to P03, P20, P22, P24 to P27, P33, P34, RESET P60 to P63 VDD = 4.5 to 6.0 V 0 0 0 VIL4 VIL5 X1, X2 XT1/P04, XT2 VDD = 4.5 to 6.0 V 0 0 0 Output voltage high Output voltage low VOL1 P01 to P03, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P64 to P67 VOH1 VDD = 4.5 to 6.0 V,IOH = -1 mA IOH = -100 A P50 to P57, P60 to P63 VDD = 4.5 to 6.0 V, IOL = 15 mA VDD = 4.5 to 6.0 V, IOL = 1.6 mA VDD = 4.5 to 6.0 V, VOL2 SB0, SB1, SCK0 open-drain pulled-up (R = 1 K ) VOL3 Input leakage current high ILIH1 VIN = VDD IOL = 400 A P00 to P03, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, RESET ILIH2 ILIH3 Input leakage current high ILIL1 VIN = 15 V X1, X2, XT1/P04, XT2 P60 to P63 P00 to P03, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, VIN = 0 V ILIL2 ILIL3 P64 to P67, RESET X1, X2, XT1/P04, XT2 P60 to P63 *1 Other than above -20 -200 -3
*2
MIN.
TYP.
MAX.
Unit
VIH1
0.7 VDD
VDD
V
VDD 15 VDD VDD VDD 0.3 VDD
V V V V V V
0
0.2 VDD 0.3 VDD 0.2 VDD 0.4 0.4 0.3
V V V V V V V V
VDD-1.0 VDD-0.5 0.4 2.0
V
0.4
V
0.2 VDD
V
0.5
V
3
A
20 80
A A
-3
A
A A A
*
1. When memory expansion mode is used by the memory expansion mode register (MM) with no on-chip pull-up resistor by mask option. 2. When pull-up resistors are not used (specified by mask option), the low-level input leakage current increases with -200 A (MAX.) under either of the following conditions. When the external device expansion function is used and a low level is input to the pin. During the 3-clock period when a read instruction is executed on port 6 (P6) and the port mode registor (PM6). The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
q w Remark
34
PD78001B(A), 78002B(A)
DC Characteristics (TA = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter Output leakage current high Output leakage current low Mask option pullup resister Software pullup resister
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
ILOH1
VOUT = VDD
3
A A
ILOL
VOUT = 0 V
-3
R1
VIN = 0 V, P60 to P63 VIN = 0 V, P01 to P03,
20
40
90
k
R2
P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67
4.5 V VDD < 6.0 V 2.7 V VDD < 4.5 V VDD = 5.0 V 10 % *1 VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 % VDD = 5.0 V 10 % VDD = 3.0 V 10 %
*2
15
40
90
k
20 7.5 0.8 1.4 550 60 35 25 5 1 0.5 0.1 0.05
500 22.5 2.4 4.2 1650 120 70 50 10 20 10 20 10
k mA mA mA
Power supply current
*3
IDD1
8.38 MHz Crystal oscillation operating mode 8.38 MHz Crystal oscillation HALT mode 32.768 kHz Crystal oscillation operating mode 32.768 kHz Crystal oscillation HALT mode XT1 = 0 V STOP mode When feedback resister is used XT1 = 0 V STOP mode When feedback resister is unused
IDD2
A A A A A A A A A
IDD3
IDD4
IDD5
IDD6
*
1. Operating in high-speed mode (when set the processor clock control register to 00H). 2. Operating in low-speed mode (when set the processor clock control register to 04H). 3. Port current are excluded.
Remark
The characteristics of a dual-function pin and a port pin are the same unless specified otherwise.
35
PD78001B(A), 78002B(A)
AC Characteristics (TA = -40 to +85 C, VDD = 2.7 to 6.0 V) (1) Basic Operation
Parameter Cycle time (Min. instruction execution time) TI input frequency TI input high/ low-level width Interrupt input high/low-level width RESET low level width tRSL tTIH tTIL tINTH tINTL INTP0 INTP1 to INTP3 KR0 to KR7 VDD = 4.5 to 6.0 V fTI TCY Symbol Operating on main system clock Operationg on subsystem clock VDD = 4.5 to 6.0 V Test Conditions VDD = 4.5 to 6.0 V MIN. 0.4 0.96 40 0 0 100 1.8 8/fsam* 10 10 10 122 TYP. MAX. 64 64 125 4 275 Unit
s s s
MHz kHz ns
s s s s s
*
In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register, selection of fsam is possible between fX/2N+1, fX/64 and fx/128 (when N = 0 to 4).
PD78001B(A), 78002B(A)
TCY vs VDD (At main system clock operation)
PD78P014 (Reference)
TCY vs VDD (At main system clock operation)
60
60
10 Cycle Time TCY [s] Operation Guaranteed Range Cycle Time TCY [s]
10 Operation Guaranteed Range
2.0 1.0 0.5 0.4
2.0 1.0 0.5 0.4
0 1 2 3 4 5 6 Supply Voltage VDD [V]
0 1 2 3 4 5 6 Supply Voltage VDD [V]
Remark
indicates TA=-40 to +40 C indicates TA=-40 to +85 C
Caution
The operation guaranteed range of the PD78001B(A), and 78002B(A) differs from that of the PD78P014.
36
PD78001B(A), 78002B(A)
(2) Read/Write Operation (TA = -40 to +85 C, VDD = 2.7 to 6.0 V)
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from RD tRDD1 tRDD2 Read data hold time RD low-level width tRDH tRDL1 tRDL2 WAIT input time from RD tRDWT1 tRDWT2 WAIT input time from WR WAIT low-level width Write data setup time Write data hold time WR low-level width RD delay time from ASTB WR delay time from ASTB ASTB delay time from tRDAST RD in external fetch Address hold time from tRDADH RD in external fetch Write data output time from RD WR delay time from write data tWDWR 0.5tCY-170 Address hold time from WR tWRADH tCY RD delay time from WAIT WR delay time from WAIT tWTRD tWTWR 0.5tCY 0.5tCY tCY+100 2.5tCY+80 2.5tCY+80 ns ns ns VDD =4.5 to 6.0 V tCY 0.5tCY tCY+60 ns ns tRDWD VDD = 4.5 to 6.0 V 10 0.5tCY-120 0.5tCY ns ns tCY tCY+50 ns tCY-10 tCY+40 ns tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR (0.5+2n)tCY +10 100 5 (2.5+2n)tCY -20 0.5tCY-30 1.5tCY -30 0 (1.5+2n)tCY-20 (2.5+2n)tCY-20 0.5tCY 1.5tCY 0.5tCY (2+2n)tCY 5 Load resistor 5 k Test Conditions MIN. 0.5tCY 0.5tCY-30 10 (2+2n)tCY-50 (3+2n)tCY-100 (1+2n)tCY-25 (2.5+2n)tCY-100 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Remarks
1. 2. 3.
tCY = TCY/4 n indicates number of waits. CL = 100 pF (CL indicates load capacitance of P40/AD0 to P47/AD7, P50/A8 to P57/A15, P64/RD, P65/WR, P66/WAIT,P67/ASTB pins).
37
PD78001B(A), 78002B(A)
(3) Serial Interface (TA = -40 to +85 C, VDD = 2.7 to 6.0 V) (a) 3-wire serial I/O mode (SCK... Internal clock output)
Parameter SCK cycle time tKCY1 3200 SCK high/low-level width tKH1 tKL1 SI setup time (to SCK) SI hold time (from SCK) SO output delay time from tKSO1 SCK C = 100 pF* 1000 ns tSIK1 tKSI1 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKCY1/2-50 tKCY1/2-150 100 400 300 ns ns ns ns ns ns Symbol Test Conditions VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. Unit ns
*
C is the load capacitance of SO output line.
(b) 3-wire serial I/O mode (SCK... External clock input)
Parameter SCK cycle time tKCY2 3200 SCK high/low-level width tKH2 tKL2 SI setup time (to SCK) SI hold time (from SCK) SO output delay time from tKSO2 SCK SCK rise, fall time tR2 When external device expansion function is used When external device expansion function is not used 1000 ns C = 100 pF* 1000 160 ns tSIK2 tKSI2 VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 400 300 ns ns ns ns ns ns Symbol Test Conditions VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. Unit ns
tF2
*
C is the load capacitance of SO output line.
38
PD78001B(A), 78002B(A)
(c) SBI mode (SCK... Internal clock output)
Parameter SCK cycle time Symbol tKCY3 Test Conditions VDD = 4.5 to 6.0 V MIN. 800 3200 SCK high/low-level width tKH3 tKL3 SB0, SB1 setup time tSIK3 (to SCK) SB0, SB1 hold time tKSI3 from SCK SB0, SB1 output delay time tKSO3 (from SCK) SB0, SB1 from SCK SCK from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width tKSB tSBK tSBH tSBL C = 100 pF* 0 tKCY3 tKCY3 tKCY3 tKCY3 1000 ns ns ns ns ns R = 1 k , VDD = 4.5 to 6.0 V 0 250 ns tKCY3/2 ns 300 ns VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V tKCY3/2-50 tKCY3/2-150 100 TYP. MAX. Unit ns ns ns ns ns
*
R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
(d) SBI mode (SCK... External clock input)
Parameter SCK cycle time tKCY4 3200 SCK high/low-level width tKH4 tKL4 SB0, SB1 setup time tSIK4 (to SCK) SB0, SB1 hold time tKSI4 (from SCK) SB0, SB1 output delay time tKSO4 from SCK SB0, SB1 from SCK SCK from SB0, SB1 SB0, SB1 high-level width SB0, SB1 low-level width SCK rise, fall time tKSB tSBK tSBH tSBL tR4 tF4 When external device expansion function is used When external device expansion function is not used 1000 ns C = 100 pF* 0 tKCY4 tKCY4 tKCY4 tKCY4 160 1000 ns ns ns ns ns ns R = 1 k , VDD = 4.5 to 6.0 V 0 300 ns tKCY4/2 ns 300 ns VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns Symbol Test Conditions VDD = 4.5 to 6.0 V MIN. 800 TYP. MAX. Unit ns
*
R and C are the load resistors and load capacitance of the SB0 and SB1 output line.
39
PD78001B(A), 78002B(A)
(e) 2-wire serial I/O mode (SCK... Internal clock output)
Parameter SCK cycle time tKCY5 3800 SCK high-level width SCK low-level width SB0, SB1 setup time tSIK5 (to SCK) SB0, SB1 hold time tKSI5 (from SCK) SB0, SB1 output delay time tKSO5 from SCK C = 100 pF* 0 1000 ns R = 1 k, VDD = 4.5 to 6.0 V 0 250 ns 600 ns 300 ns tKH5 tKL5 R = 1 k, C = 100 pF* tKCY5/2-50 tKCY5/2-50 ns ns ns Symbol Test Conditions VDD = 4.5 to 6.0 V MIN. 1600 TYP. MAX. Unit ns
*
R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
(f) 2-wire serial I/O mode (SCK... External clock input)
Parameter SCK cycle time tKCY6 3800 SCK high-level width SCK low-level width SB0, SB1 setup time tSIK6 (to SCK) SB0, SB1 hold time tKSI6 (from SCK) SB0, SB1 output delay time tKSO6 from SCK SCK rise, fall time tR6 tF6 C = 100 pF* When external device expansion function is used When external device expansion function is not used 1000 ns 0 1000 160 ns ns R = 1 k, VDD = 4.5 to 6.0 V 0 300 ns tKCY6/2 ns 100 ns tKH6 tKL6 650 800 ns ns ns Symbol Test Conditions VDD = 4.5 to 6.0 V MIN. 1600 TYP. MAX. Unit ns
*
R and C are the load resistors and load capacitance of the SCK0, SB0 and SB1 output line.
40
PD78001B(A), 78002B(A)
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
Clock Timing
1/fX
tXL
tXH VDD - 0.5 V 0.4V
X1 Input
1/fXT
tXTL
tXTH VDD - 0.5 V 0.4V
XT1 Input
TI Timing
1/fTI
tTIL TI1, TI2
tTIH
41
PD78001B(A), 78002B(A)
Read/Write Operation External fetch (no wait):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tASTH ASTB
Upper 8-Bit Address tADD1 Hi-z Operation Code tRDD1 tRDADH tRDAST
tADH
RD tASTRD tRDL1 tRDH
External fetch (wait insertion):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tASTH ASTB
Upper 8-Bit Address
tADD1 Hi-z tRDD1 tADH tRDAST Operation Code tRDADH
RD tASTRD tRDL1 tRDH
WAIT tRDWT1 tWTL tWTRD
42
PD78001B(A), 78002B(A)
External data access (No wait):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tADH tASTH ASTB
Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
RD tASTRD tRDL2
tRDWD
tWDS tWDWR
tWDH tWRADH
WR tASTWR tWRL1
External data access (Wait insertion):
A8-A15 Lower 8-Bit Address AD0-AD7 tADS tADH tASTH ASTB
Upper 8-Bit Address
tADD2 Hi-z tRDD2 tRDH Read Data Write Data Hi-z
tASTRD RD tRDL2 tRDWD WR tASTWR tWRL1 tWRADH tWDS tWDWR tWDH
WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR
43
PD78001B(A), 78002B(A)
Serial Transfer Timing 3-wire serial I/O mode:
tKCY 1,2
tKL1,2 tR2 SCK tSIK1,2 tKSI1,2
tKH1,2 tF2
SI tKSO1,2
Input Data
SO
Output Data
SBI mode (Bus release signal transfer):
tKCY3,4 tKL3,4 tR4 SCK tKSB tSBL tSBH tSBK tSIK3,4 tKSI3,4 tKH3,4 tF4
SB0, SB1 tKSO3,4
SBI mode (Command signal transfer):
tKCY3,4 tKL3,4 tR4 SCK tKSB tSBK tSIK3,4 tKSI3,4 tKH3,4 tF4
SB0, SB1 tKSO3,4
44
PD78001B(A), 78002B(A)
2-wire serial I/O mode:
tKCY5,6 tKL5,6 tR6 SCK tSIK5,6 tKSO5,6 SB0, SB1 tKSI5,6 tKH5,6 tF6
45
PD78001B(A), 78002B(A)
Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85 C)
Parameter Data retention VDDDR supply voltage Data retention supply current Release signal set time Oscillation stabilization tWAIT wait time Release by interrupt * VDDDR = 2.0 V Subsystem clock stop and feed-back resister disconnected 0 Release by RESET 218/fx 2.0 6.0 V Symbol Test Conditions MIN. TYP. MAX. Unit
IDDDR
0.1
10
A s s s
tSREL
* In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection of 213/fx and 215/fx to 218/fx is possible.
Data Retention Timing (STOP Mode Release by RESET)
HALT Mode STOP Mode Operating Mode
Data Retension Mode
VDD STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retension Mode
VDD STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
46
PD78001B(A), 78002B(A)
Interrupt Input Timing
tINTL INTP0-INTP2
tINTH
tINTL
INTP3
RESET Input Timing
tRSL
RESET
47
PD78001B(A), 78002B(A)
12. CHARACTERISTIC CURVE (REFERENCE VALUES)
IDD vs VDD (Main System Clock : 8.38 MHz)
10.0
(TA=25C) PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT (X1 Oscillation, XT1 Oscillation)
5.0
1.0
0.5
Supply Current IDD [mA]
0.1 PCC=B0H 0.05 HALT (X1 Stop, XT1 Oscillation) STOP (X1 Stop, XT1 Oscillation)
0.01
0.005
f X =8.38MHz f XT=32.768kHz
0.001 0
2
3
4
5
6
7
8
Supply Voltage VDD [V]
48
PD78001B(A), 78002B(A)
IDD vs VDD (Main System Clock : 4.19 MHz)
10.0
(TA=25C)
5.0
PCC=00H PCC=01H PCC=02H PCC=03H PCC=04H PCC=30H HALT (X1 Oscillation, XT1 Oscillation)
1.0
0.5
Supply Current IDD [mA]
0.1 PCC=B0H 0.05
HALT (X1 Stop, XT1 Oscillation) STOP (X1 Stop, XT1 Oscillation)
0.01
0.005
f X =4.19MHz f XT=32.768kHz
0.001 0
2
3
4
5
6
7
8
Supply Voltage VDD [V]
49
PD78001B(A), 78002B(A)
IDD vs fX
(VDD = 3 V, TA = 25 C)
5 PCC=00H
Supply Current IDD [mA]
4
3 PCC=01H
2 PCC=02H PCC=03H PCC=04H HALT (X1 Oscillation)
1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
Clock Oscillator Frequency fX [MHz]
IDD vs fX
12 11 10 9 PCC=00H
Supply Current IDD [mA]
(VDD = 5 V, TA = 25 C)
8 7 6 PCC=01H 5 4 3 2 1 0 PCC=02H PCC=03H PCC=04H HALT (X1 Oscillation)
0
1
2
3
4
5
6
7
8
9
10
11
12
Clock Oscillator Frequency fX [MHz]
50
PD78001B(A), 78002B(A)
VOL vs IOL (Port 0, 2 to 5, P64 to P67)
(TA=25 C) VDD=5 V VDD= 6 V VDD=4 V VDD=3 V
30
VOL vs IOL (P60 to P63)
(TA=25 C)
30
VDD=6 V
VDD=5 V
VDD=4 V
Output Current Low IOL [mA]
20
Output Current Low IOL [mA]
VDD=3 V 20
10
10
0
0
0.5
1.0
Output Voltage Low VOL [V]
0 0 0.5 1.0 Output Voltage Low VOL [V]
VOL vs IOL (Port 1)
(TA=25 C)
VOH vs IOH (Port 0 to 5, P64 to P67)
(TA=25 C)
30
VDD=6 V VDD=5 V
Output Current High IOH [mA]
VDD=4 V VDD=3 V
-10
VDD=5 V VDD=4 V VDD=6 V VDD=3 V
Output Current Low IOL [mA]
20
-5
10
0
0
0
0 0.5 1.0 Output Voltage Low VOL [V]
0.5
1.0
Output Voltage High VDD - VOH [V]
51
PD78001B(A), 78002B(A)
13. PACKAGE DRAWINGS DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (1/2)
64-PIN PLASTIC SHRINK DIP (750 mil)
64 33
1 A
32
K L
J
I
F D
G
H
N
M
C
B
M
R
NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R
MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15
INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1
Caution
Dimensions and materials of ES products are different from those of mass-production products. Refer to DRAWINGS OF ES PRODUCT PACKAGES (1/2).
52
PD78001B(A), 78002B(A)
DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (2/2)
64-PIN PLASTIC QFP (s 14) s
A B
48 49
33 32 detail of lead end
C
D
S
64 1
17 16
F
G
H
IM
J K
P
N
L P64GC-80-AB8-3 ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.6 0.4 14.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.35 0.10 0.15 0.8 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.55 0.1 0.1 2.85 MAX. INCHES 0.693 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.071 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.100 0.004 0.004 0.112 MAX.
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
Caution
Dimensions and materials are different from those of mass-production products. Refer to DRAWINGS OF ES PRODUCT PACKAGES (2/2).
M
55
Q
53
PD78001B(A), 78002B(A)
DRAWINGS OF ES PRODUCT PACKAGES (1/2)
64PIN CERAMIC SHRINK DIP (SEAM WELD) (750 mil)
64
33
1 A
32 K L
J
I
F D
H
B
NM C M 0~15
G
P64D-70-750A1 NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N MILLIMETERS 58.16 MAX. 1.521 MAX. 1.778 (T.P.) 0.46 0.05 0.8 MIN. 3.5 0.3 1.02 MIN. 3.14 5.08 MAX. 19.05 (T.P.) 18.8 0.25 0.05 0.25 INCHES 2.290 MAX. 0.060 MAX. 0.070 (T.P.) 0.018 0.002 0.031 MIN. 0.138 0.012 0.040 MIN. 0.124 0.200 MAX. 0.750 (T.P.) 0.740 0.010 -0.003 0.01
+0.002
54
PD78001B(A), 78002B(A)
DRAWINGS OF ES PRODUCT PACKAGES (2/2)
64 PIN CERAMIC QFP (14 x 14) (FOR ES)
A B
48 49
33 32
64 1
17 16
F
G
H
J K
Q M
D
C
(Bottom View)
X64B-80A-1 INCHES 0.866 0.016 0.551 0.551 0.866 0.016 0.039 0.039 0.013 0.031 (T.P.) 0.157+0.007 -0.006 0.01 0.119 MAX. 0.022 0.039 0.047
ITEM A B
MILLIMETERS 22.0 0.4 14.0 14.0 22.0 0.4 1.0 1.0 0.32 0.8 (T.P.) 4.0 0.15 0.25 3.0 MAX. 0.55 1.0 1.2
T
C D F G
U V
H J K M Q T U V
55
PD78001B(A), 78002B(A)
14. RECOMMENDED SOLDERING CONDITIONS
The PD78001B(A)/78002B(A) should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our sales personnel.
Table 14-1 Surface Mounting Type Soldering Conditions
PD78001BGC(A)-xxx-AB8 : PD78002BGC(A)-xxx-AB8 :
Soldering Method Infrared reflow
64-Pin Plastic QFP (s 14 mm) s 64-Pin Plastic QFP (s 14 mm) s
Recommended Condition Symbol IR35-00-2
Soldering Conditions Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: Twice max. < Points to note > (1) Start the second reflow after the device temprature by the first reflow returns to normal. (2) Flux washing by the water after the first reflow should be avoided.
VPS
Package peak temperature: 215C, Duration: 40 sec. max. (at 200C or above) Number of times: Twice max. < Points to note > (1) Start the second reflow after the device temprature by the first reflow returns to normal. (2) Flux washing by the water after the first reflow should be avoided.
VP15-00-2
Pin part heating Pin temperature: 300C max., Duration: 3 sec. max. (per device side)
--
Caution
Use of more than one soldering method should be avoided (except in the case of pin part heating).
Table 14-2 Insertion Type Soldering Conditions
PD78001BCW(A)-xxx : PD78002BCW(A)-xxx :
Soldering Method Wave soldering (Pin only) Pin part heating
64-Pin Plastic Shrink DIP (750 mil) 64-Pin Plastic Shrink DIP (750 mil)
Soldering Conditions Solder bath temperature: 260C max., Duration: 10 sec. max. Pin temperature: 300C max., Duration: 3 sec. max. (per pin)
Caution
Wave soldering is only for the pins in order that jet solder can not contact with the chip directly.
56
PD78001B(A), 78002B(A)
APPENDIX A. DEVEROPMENT TOOLS
The following development tools are available for system development using the PD78001B(A), 78002B(A). Language Processing Software
RA78K/0*1, 2, 3 CC78K/0*1, 2, 3 DF78002*1, 2, 3 CC78K/0-L
*1, 2, 3
78K/0 series common assembler package 78K/0 series common C compiler package
PD78002 subseries device file
78K/0 series common C compiler library source file
PROM Programming Tools
PG-1500 PA-78P014CW PA-78P014GC PG-1500 controller*1, 2 PROM programmer Programmer adapter connected to PG-1500 PG-1500 control program
Debugging Tools
IE-78000-R IE-78000-R-BK IE-78014-R-EM EP-78240CW-R EP-78240GC-R EV-9200GC-64 SD78K/0*1, 2 SM78K/0 DF78002
*4, 5, 6
78K/0 series common in-circuit emulator 78K/0 series common break board
PD78002/78014 subseries evaluation emulation board
Emulation probe common to PD78244 subseries Socket to be mounted on user system board created for the 64-pin plastic QFP IE-78000-R screen debugger 78K/0 series common system simulator
*1, 2, 4, 5
PD78002 subseries device file
Enbedded OS
MX78K/0*1, 2, 3, 6 78K/0 series common enbedded OS
Fuzzy Inference Development Support System
FE9000*1/FE9200*5 FT9080 /FT9085 FI78K0*1, 2 FD78K0*1, 2
*1 *2
Fuzzy knowledge data creation tool Translator Fuzzy inference module Fuzzy inference debugger
* 1. PC-9800 series (MS-DOSTM) based. 2. IBM PC/ATTM (PC DOSTM) based. 3. HP9000 series 300TM, HP9000 series 700TM (HP-UXTM) based, SPARCstationTM, (Sun OSTM) based, EWS-4800 series (EWS-UX/V) based. 4. PC-9800 series (MS-DOS + WindowsTM) based. 57
PD78001B(A), 78002B(A)
5. IBM PC/AT (PC DOS + Windows) based. 6. Under development. Remarks 1. For development tools manufactured by a third party, see the "78K/0 Series Selection Guide" (IF1185). 2. RA78K/0, CC78K/0, SD78K/0, and SM78K/0 are used in combination with DF78002.
58
PD78001B(A), 78002B(A)
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document Name User's Manual 78K/0 Series User's Manual - Instruction Application Note Basic I Basic II Document No. (Japanese) IEU-788 IEU-849 IEA-715 IEA-740 Document No. (Engligh) IEU-1334 IEU-1372 IEA-1288 IEA-1299
Development Tools Documents (User's Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor CC78K Series C Compiler Operation Language PG-1500 PROM Programmer PG-1500 Controller IE-78000-R IE-78000-R-BK IE-78014-R-EM EP-78240 SD78K/0 Screen Debugger Beginner's guide Reference Document No. (Japanese) EEU-809 EEU-815 EEU-817 EEU-656 EEU-655 EEU-651 EEU-704 EEU-810 EEU-867 EEU-805 EEU-986 EEU-852 EEU-816 Document No. (Engligh) EEU-1399 EEU-1404 EEU-1402 EEU-1280 EEU-1284 EEU-1335 EEU-1291 EEU-1398 EEU-1427 EEU-1400 In preparation EEU-1414 EEU-1413
Embedded Software Documents (User's Manual)
Document Name Fuzzy Knowledge Data Creation Tool 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System - Translator Document No. (Japanese) EEU-892 EEU-862 Document No. (Engligh) EEU-1438 EEU-1444
Caution
These documents above are subject to change without notice. Besure to use the latest document for designing your system.
59
PD78001B(A), 78002B(A)
Other Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grade on NEC Semiconductor Devices Semiconductor Device Quality Guarantee Guide Document No. (Japanese) IEI-635 IEI-616 IEI-620 MEI-603 Document No. (Engligh) IEI-1213 IEI-1207 IEI-1209 MEI-1202
Caution
These documents above are subject to change without notice. Besure to use the latest document for designing your system.
60
PD78001B(A), 78002B(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
61
PD78001B(A), 78002B(A)
[MEMO]
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. FIP is a registered trademark of NEC Corporation. IEBus is a trademark of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc.
M4 94.11

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